A Design Tool for Modeling Asynchronous Dynamic Logic

For high performance designs, dynamic logic techniques have to be considered due to the promising high reachable frequencies. Such a technique is the True Single Phase Clock (TSPC) logic that allows designing circuits with standard cells and high speed potential. However, the disadvantages are a difficult clock tree design and high power consumption. Asynchronous logic has the potential to solve these problems. The used technique in this work, Asynchronous Chain-TSPC logic, assembles small asynchronous chains of dynamic logic gates into one period of the global clock. The results are shorter latency for calculations, power reduction due to reduced overall input load and due to no need for latches as well as a simpler clock distribution network with increased clock skew tolerance and reduced clock load. Current high level synthesis tools do not support automated synthesis and verification of asynchronous dynamic logic. Thus, this contribution presents a complete design flow for Asynchronous Chain-TSPC logic. We use the toolset DYNAMIC, which realizes a transformation of a combinational circuit into a pipelined structure and the tool AC-DYNAMIC which implements the conversion of a pipelined structure into an asynchronously clocked structure. Furthermore, AC-DYNAMIC is capable of verifying the timing behavior and undertakes optimizations. The design flow is exemplarily applied for a 32bit-single-error-correcting circuit.